1. Field of the Invention
The present invention relates to a memory device. In particular, the present invention provides a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device wherein a direct polyimide etching (‘DPE’) process reducing the two steps of a masking process to one step is employed, a dummy contact hole is formed on a metal line in a scribe lane of a semiconductor substrate, and then a passivation layer filling up the dummy contact hole is formed to mechanically support thermal stress generated in an annealing process, thereby preventing a crack as a particle source in a subsequent packaging process from occurring.
2. Discussion of the Related Art
FIGS. 1a and 1b are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
In manufacturing a MOSFET device, a transistor and a capacitor are formed, and then a metal line to connect them with an outer circuit is formed. Thereafter, a passivation layer is formed in order to protect the device.
Next, a repair and process of forming and patterning a polymide to protect the semiconductor device is performed in order to open a pad and fuse box region for connecting a package. The repair and the process of forming and patterning a polymide is performed respectively using a repair mask 20 and a polymide mask 30 (referring to FIG. 1a). The repair and process of forming and patterning a polymide is required to two steps of making masks such as a repair mask and a polymide mask.
Recently, a direct polyimide etching (‘DPE’) process for opening a pad and fuse box region using one mask 40 instead of the repair and process of forming and patterning a polymide with two steps of a mask process has been proposed in order to reduce the number of process steps (referring to FIG. 1b).
FIGS. 2a and 2b are a cross-sectional view and a photograph showing a problem according to the conventional method for manufacturing a semiconductor device, respectively.
The DPE process makes the process for manufacturing a semiconductor device simple and improves a refresh characteristic of DRAM. However, referring to FIGS. 2a and 2b, a passivation layer 70 without an open area is deposited after a formation process for a metal line 50, and then an annealing process is performed onto the semiconductor substrate in an ambient of H2/N2. When a thin film deposited at a high temperature is cooled at a room temperature or an annealing process is sequentially performed onto the deposited thin film and a cooling process, the thin film receives a thermal stress from the annealing process. As a result, a crack such as a circle-shaped crack ‘A’, which serves as a particle source during a packaging process, is generated on the passivation layer 70.
According to a conventional method for manufacturing a semiconductor device, the passivation layer is formed on the metal line, and then the annealing process is performed onto the semiconductor substrate using H2/N2 to apply the thermal stress to a SOG (spin on glass (‘SOD’) layer for a passivation layer, thus generating a crack which serves as a particle source in a subsequent packaging process. As a result, the crack prevents the metal line from being connected, thus reducing the product yield for manufacturing the semiconductor device.